1. Field of the Invention
The present invention is related to multilayered circuit structure. More specifically, the present invention provides a structure and method for producing or forming a multilayered circuit structure.
2. Description of the Prior Art
Multilayer circuit structures can be used to electrically communicate two or more electrical devices such as two or more computer chips. Multilayer circuit structures typically contain multiple conductive layers separated by one or more dielectric layers. Via structures disposed in apertures in the dielectric layers provide conductive paths so that electrical signals can pass from one conductive layer to another conductive layer. Multiple via structures in successive dielectric layers can be used to form a conductive path from an inner region to an outer region of a multilayer circuit structure.
The via structures in successive dielectric layers can be staggered in a multilayer circuit structure. For example, as shown in FIG. 37, a plurality of staggered via structures 110 are in electrical communication with each other. The staggered conductive path formed by the via structures 110 can provide communication between a core structure 120 and an outer surface of the multilayer circuit structure 100. Each of the via structures 110 shown in FIG. 37 is in the form of a conductive coating on an aperture wall in a dielectric layer. Unfortunately, staggering the via structures can consume valuable area in a multilayer circuit structure and can increase the signal run length. This can decrease the density of the circuitry in a multilayer circuit structure. Moreover, the metal coating of via structures of the type shown in FIG. 37 is thin. Open circuits can form if the coating is not thick enough or is not uniform.
A patentability investigation was conducted and the following U.S. Patents were discovered: U.S. Pat. No. 4,824,802, to Brown et al.; U.S. Pat. No. 5,188,702, to Takayama et al.; U.S. Pat. No. 5,454,928, to Rogers et al.; U.S. Pat. No. 5,495,665, to Carpenter et al.; U.S. Pat. No. 5,5291,504, to Greenstein et al.; U.S. Pat. No. 5,707,893, to Bhatt et al.; U.S. Pat. No. 5,763,324, to Nogami; U.S. Pat. No. 5,817,574, to Gardner; U.S. Pat. No. 5,819,406, to Yoshizawa et al.; U.S. Pat. No. 5,851,910, to Hsu et al.; U.S. Pat. No. 5,879,568, to Urasaki et al.; U.S. Pat. No. 5,891,606, to Brown; U.S. Pat. No. 5,925,206, to Boyko et al.; U.S. Pat. No. 5,939,789, to Kawai et al.; U.S. Pat. No. 5,998,291, to Bakhit et al.; and U.S. Pat. No. 6,071,814, to Jang.
U.S. Pat. No. 4,824,802 discloses a method to provide an electrical connection between conductive layers separated by an insulative layer in integrated circuit devices. An intermediary metal, such as molybdenum or tungsten, is deposited by one or more methods so as to fill an opening in the insulative layer. A planarization resist may be applied on the substrate and the resulting configuration is planarizingly etched down to the insulative layer so as to provide a metal plug conductive layer. Deposition is by sputtering, evaporation, or by either selective or non-selective chemical vapor deposition.
U.S. Pat. No. 5,188,702 discloses an anisotropic conductive film comprising an insulating film having the fine through-holes independently piercing the film in the thickness direction, each of the through-holes being filled with a metallic substance in such a manner that at least one end of each through-hole has a bump-like projection of the metallic substance having a bottom area larger than the opening of the through-hole. The metallic substance serves as a conducting path which is prevented from falling off.
U.S. Pat. No. 5,454,928 discloses a method of forming solid metal vias extending between the top and bottom surfaces of a substrate with the ends of the vias being substantially coplanar with the top and bottom surfaces. The method includes the steps of forming holes through the substrate, plating the interior of the holes with excess metal to fill the holes and extend beyond the ends of the holes, heating the substrate to cause the metal to melt and consolidate to form solid vias with domed ends, and lapping the top and bottom surfaces of the substrate to remove the domes. Conductive layers may then be formed over the vias. These layers may have windows over a portion of each via to provide an escape route for expanding fluids during further processing of the substrate.
U.S. Pat. No. 5,495,665 discloses a process for connecting at least two electrically conductive patterns through a dielectric material by a landless electrical connection. The process includes providing a composite containing a dielectric substrate having a conductive plane on at least one of its major surfaces and a temporary support layer covering the conductive plane. Blind vias are provided in the dielectric substrate and are plated with an electrically conductive material. The temporary support layer is removed thereby providing a landless electrical connection through the dielectric material.
U.S. Pat. No. 5,529,504 discloses a microconnection device and a method of forming such a device include providing an array of electrically interconnected conductors within through holes of an insulative flexible film. Each conductor has a microbump. Since the conductors are interconnected, the microbumps define a cluster for contact with a single contact, such as an input/output pad of a semiconductor device. The flexible film includes a cavity at the central region of the cluster, thereby enhancing the flexibility of the film. By applying a load force within the central region of the cluster, the flexible film is caused to bend in a manner to achieve load compliance and a lateral scrub for removing contaminants, oxides and the like at the interface of the microbumps and the contact. A top bump that is misaligned with the microbumps may be formed to ensure proper localization of the load force within the central region.
U.S. Pat. No. 5,707,893 discloses a process for making a circuitized substrate which is treated with an additive and a subtractive metallization process. The disclosed process produces substrates including conductive features, e.g., high density circuit lines and chip heat-sinking pads, of two different degrees of resolution.
U.S. Pat. No. 5,763,324 discloses conductors in contact holes. A first resist is coated on a conductor provided selectively in a contact hole formed in an insulating film provided on a semiconductor substrate, as well as on the insulating film, and a resultant structure is flattened. The first resist and the conductor are removed with their portions being left. A second resist is coated on the conductor and insulating film and a resultant structure is flattened. The second resist and the conductor are removed until the insulating film is exposed.
U.S. Pat. No. 5,817,574 discloses a high reliability interconnection structure for an integrated circuit. The interconnection structure of the present invention is formed on a first insulating layer which in turn is formed on a silicon substrate. A first multilayer interconnection comprises a first aluminum layer, a first refractory metal layer, and a second aluminum layer is formed on the first insulating layer. A second insulating layer is formed over the first multilayer interconnection. A conductive via is formed through the second insulating layer and recessed into the first multilayer interconnection wherein a portion of the via extends above the second insulating layer. A second interconnection is formed on the second insulating layer and on and around the portion of the via extending above the second insulating layer.
U.S. Pat. No. 5,819,406 discloses a method for producing an electrical circuit member by the steps of: positioning and arranging first and second electrical circuit parts having plural electrical connecting portions to be spaced and oppose each other, preparing an electrical connecting member having a plurality of electrical conductive members, and applying an adhesive to at least one side of the electrical connecting member including the electrical conductive members. The electrical connecting member with the adhesive is inserted between the first and second electrical circuit parts, and a pressing force is applied so that the first and second electrical parts contact the ends of the electrical conductive members.
U.S. Pat. No. 5,851,910 discloses a method of fabricating a bonding pad window by the steps of: providing a substrate with a metal layer, forming a dielectric layer over the metal layer, defining the dielectric layer with a first mask to form a via, forming a plug in the via, and forming a second metal layer over the plug and the dielectric layer. The second metal layer is patterned to expose the dielectric layer, and a passivation layer is formed over the second metal layer. The passivation layer is then defined with the first mask to form the bonding pad window.
U.S. Pat. No. 5,879,568 discloses a multilayer printed circuit board produced by a process comprising the steps of coating a thermosetting resin varnish compounded with electrically insulating whiskers on a roughened side of a copper foil, semi-curing the resin by heating to form a thermosetting resin layer, integrally laminating it on an interlayer board in which plated through-holes and conductor circuits have been formed, and roughening the cured thermosetting resin layer on the via hole wall surfaces with a roughening agent.
U.S. Pat. No. 5,891,606 discloses a process for forming a multilayered circuit structure entailing the use of a fill material that forms a conductive connection between the layers of the circuit structure and photodefinable resins that form permanent dielectric layers and plateable surfaces of the circuit structure. The method includes forming a through-hole in a substrate, and then filling the through-hole with the fill material containing a metal that is catalytic to electroless copper. The fill material forms an electrical connection having oppositely-disposed connection surfaces that are coextensive with opposite surfaces of the substrate. A first photodefinable dielectric layer is then formed on each surface of the substrate, including the connection surfaces, and openings are photoimaged and developed in the dielectric layers to expose a portion of each connection surface. A second dielectric layer is then formed over each of the first dielectric layers and the exposed portions of the connection surfaces, with an opening being formed in each of the second dielectric layers to re-expose the portions of the connection surfaces and contiguous surface portions of the first dielectric layers. The exposed surface portions of the first dielectric layers and the exposed portions of the connection surfaces are then electrolessly plated with copper to form conductor traces on each side of the substrate. As a result, the traces electrically contact the connection surfaces, such that traces on opposite sides of the circuit structure are interconnected with the connection formed by the fill material in the through-hole.
U.S. Pat. No. 5,925,206 discloses a method of preparing blind vias in printed circuit boards. The method allows for the drilling of holes for connection in insulating layers prior to laminating insulating layers together. Each insulative layer is prepared with patterned conductive wiring and holes are drilled through the layer at points where wiring is to connect to another level of wiring. Layers are aligned, using mechanical, optical, or other alignment mechanisms, and subsequently laminated together. The holes are plated with conductor after lamination to form an electrical connection.
U.S. Pat. No. 5,939,789 discloses a multilayer substrate which is fabricated by laminating a plurality of substrates. Each substrate comprises an insulation film, a plurality of via holes which pass through the upper surface to the lower surface of the insulation film, a wiring which is provided on the upper surface of the insulation film and the via holes. A bonding member is provided on the lower surfaces of the via holes and is electrically connected with the via holes. A bonding layer is provided on the upper surface of the insulation film where the wiring is formed.
U.S. Pat. No. 5,998,291 discloses a method of fabricating high density multilayer interconnect structures by the steps of securing a top surface of an HDMI decal fabricated on a rigid substrate to a protective film layer which is in turn adhesively secured to a flat carrier. This structure is then demounted or delaminated from the rigid substrate. The bottom of the HDMI decal, with the protective film layer and flat carrier attached thereto, is secured to a mounting substrate using a relatively thick adhesive layer. After the HDMI decal is adhesively secured to the mounting substrate, the carrier and protective film layer are removed. The top surface of the HDMI decal remains flat after it is secured to the mounting substrate, and therefore connection of integrated circuit chips to contact pads on the top surface of the decal is ensured because this surface is flat.
U.S. Pat. No. 6,071,814 discloses a method of removing a seed layer 30 from areas over an insulting layer 20 where metal lines and pads will not be formed so that electroplated metal 50 can be chemical-mechanical polished without metal residue problems 151 and dishing problems. The seed layer 30 is patterned to remove areas 40 of seed layer 30 that are not near the trenches 24.
It would be desirable to provide a method for efficiently producing a reliable high-density multilayer circuit structure in a cost effective manner.